Senior Substrate Layout Design engineer

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Piper Companies is seeking a <strong>Senior Substrate Layout Designer</strong> who will be responsible for leading the design of advanced multi-die substrate packages. The layout designer will be <strong>onsite 5 days </strong> a week in <strong> Saratoga, CA.</strong><br><br><strong> Responsibilities for the Substrate Layout Designer include: </strong><br><br> - Lead the end-to-end physical layout of high-density, multi-die substrate design. <br><br> - Design and optimize bump maps, breakout routing, via structures, and layer stack-ups. <br><br> - Collaborate with ASIC, signal integrity, and power teams to ensure clean escape routing and breakout strategies <br><br> - Evaluate routing feasibility in co-design environments, considering die floorplans and mechanical constraints. <br><br> - Drive DRC, DFM, and manufacturing rule checks to ensure fabrication readiness <br><br> - Interface with substrate vendors and OSATs for tape-out and manufacturability validation. <br><br> - Conduct technical reviews and iterate on layout improvements with internal and external stakeholders<br><br><strong> Requirements for the Substrate Layout Designer include: </strong><br><br> - 8+ years of experience in substrate layout design for high-performance IC packaging <br><br> - Proven experience expertise in organic substrate design from silicon to BGA <br><br> - Deep understanding of chiplet-based, multi-die, and advanced packaging (FPGA, CPU, CPU, MCM, CoWoS) <br><br> - Strong collaboration skills with ASIC, signal, and power teams <br><br> - Proficiency in Cadence Allegro APD and AutoCAD <br><br> - Experience working with OSATs and substrate supplies <br><br> - Bachelor's degree in Electrical Engineering or equivalent experience.<br><br><strong> Compensation for the Substrate Layout Designer includes: </strong><br><br> - Salary range: $190,000 - $255,000 <br><br> - Comprehensive benefits: Medical, Dental, Vision, 401k, PTO, holidays, and sick leave as required by law.<br><br>Keywords: Substrate layout, substrate, package substrate design, multi-die packaging, chiplet integration, CoWoS, MCM, BGA, FPGA, CPU, GPU, High-density interconnect, escape routing, signal integrity, power integrity, organic substrate, substrate tape-out, substrate DRC, cadence allegro APD, autocad, cadence SiP layout, EDA tools, Layout verification tools, ASIC, OSAT, mechanical co-design, floorplanning, design reviews<br><br>#LI-BH1 <br><br> #LI-ONSITE<br><br>This job is open for applications on 7/3/2025. Applications for this job will be accepted for at least 30 days from the posting date.

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